1. Field of the Invention
This invention pertains to low dielectric constant materials, and, in particular, to fluorinated amorphous carbon.
2. Discussion of the Related Art
As device integration densities rise and circuit dimensions shrink, certain problems are encountered. For example, the smaller line dimensions increase the resistivity of the metal lines, and the narrower interline spacing increases the capacitance between the lines. This increased resistance and capacitance causes problems in propagation delay, crosstalk noise, and power dissipation. Moreover, as the device speed increases due to smaller feature sizes, the resistance-capacitance (RC) delay caused by the increased resistivity and capacitance will tend to be the major fraction of the total delay (transistor delay+interconnect delay) limiting the overall chip performance. It is therefore desirable to reduce the increased resistance and capacitance in integrated circuit applications.
To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD), as well as alternative architectures, have been proposed to replace the current SiO.sub.2 -based interconnect technology. These alternative architectures will require the introduction of low dielectric constant (.kappa.&lt;3) materials as the interlayer dielectric and/or low resistivity conductors such as copper.
To implement low .kappa. materials to replace SiO.sub.2, two basic approaches are being developed for future interconnect architectures. The first is to improve the current process, in which metal wiring is first patterned, and then a low-.kappa. dielectric material is either (a) deposited over the entire substrate and planarized to the level of the metal wiring or (b) deposited directly next to the patterned lines.
The second approach is based on the damascene process, in which the metal is deposited into wiring channels patterned into a dielectric material. The damascene process is particularly well-suited for implementation of Cu metallization. A typical damascene process is reflected in FIGS. 1A-1C. Insulating layer 12 is deposited onto a previously deposited insulating substrate 10. As reflected in FIG. 1A, a photoresistive pattern 14 is formed on the insulating layer 12, and openings are then etched in the insulating layer 12. As shown in FIG. 1B, a conductive metal 16, e.g., aluminum, is then deposited in the trenches to form wiring, generally by sputtering or chemical vapor deposition. The deposited metal 16 is planarized down to the level of the insulating layer 12 to form delineated wiring, and the steps are repeated, as reflected in FIG. 1C to form a multilayer structure, with vias 18 connecting the wiring 16. A so-called dual damascene process also exists. As reflected in FIGS. 2A-2C, the dual damascene process involves the simultaneous formation of a conductive via and a conductive wiring, and thus requires less steps than a single damascene process. Specifically, as shown in FIG. 2A, an insulating layer 22 is deposited on a previously deposited insulating substrate 20, and is then patterned by conventional photolithographic methods to form first openings 24 that are the intended width of the via. As shown in FIG. 2B, a photoresist layer 26 is then deposited to form second openings 28 that are the intended width of the wiring trench. Etching, typically reactive ion etching (RIE), is conducted to form the via and wiring trenches. As shown in FIG. 2C, a conductive metal 32 is then deposited by a method such as sputtering or chemical vapor deposition to simultaneously form the vias and wiring.
It is desired that new low .kappa. materials exhibit a variety of electrical, chemical, mechanical and thermal properties. These properties include low dielectric constant, high thermal stability, good adhesion, low stress, good mechanical strength, matched CTE (coefficient-of-thermal-expansion) with silicon, etchability and etch selectivity, low moisture absorption, high thermal conductivity, low leakage current, high breakdown strength, and manufacturability.
A variety of low .kappa. materials have been proposed to meet some or all of these criteria. The materials are typically produced by chemical vapor deposition (CVD) or by spin-on coating. Materials produced by CVD include fluorinated SiO.sub.2 glass (.kappa.=3.5), fluorinated amorphous carbon, and polymers such as the parylene and polynaphthalene families, and polytetrafluoroethylene (PTFE) (.kappa.=2.7-3.5 for nonfluorinated polymers and 1.8-3.0 for fluorinated polymers). (Amorphous carbon indicates a material having a mixture of sp.sup.1, sp.sup.2, and Sp.sup.3 bonded carbon, i.e., a mixture of carbyne, graphite, and diamond structures, respectively, in which no more than 40% of the carbon bonds are Sp.sup.3.) Materials deposited by spin-on coating include organic polymers, inorganic polymers, inorganic-organic hybrids, and porous materials such as xerogels or aerogels. Organic materials typically offer lower dielectric constants than inorganic materials but exhibit disadvantageous properties such as low thermal stability, low mechanical strength, low resistance to oxygen plasma, and poor adhesion, and also tend to cause via poisoning (i.e., detrimentally affect the reliability of the conductive vias).
Fluorinated amorphous carbon (a-C:F) has attracted particular attention recently as a promising candidate for low .kappa. ILD material. Amorphous C:F layers deposited by chemical vapor deposition techniques, using source compounds of hydrocarbons (such as CH.sub.4, C.sub.2 H.sub.2) and fluorocarbons (such as CF.sub.4, C.sub.2 F.sub.6, C.sub.4 F.sub.8), have exhibited useful dielectric constants. In particular, a-C:F layers with a dielectric constants of 2.1 to 2.3 have been deposited with both parallel-plate plasma enhanced CVD and high density plasma (HDP) CVD. (See K. Endo and T. Tatsumi, J. Appl. Phys., 78, 1370 (1995); Y. Matsubara et al., IEEE IEDM 1996, p. 14.6.1; A. Grill et al., Mat. Res. Soc. Symp. Proc., Vol. 443, p. 155 (1997); and K. Endo and T. Tatsumi, Appl. Phys. Lett. 68, 2864 (1996).)
While the CVD process offers useful results, the process disadvantageously involves complicated chemistries, i.e., chemical reactions of different species, requires elevated temperatures to provide appropriate energy and kinetics for the chemical reactions, and is prone to impurity and particle contamination caused by gas phase reactions. Moreover, the a-C:F layers produced by CVD exhibit poor adhesion on SiO.sub.2, and therefore require an additional buffer layer to promote adhesion. The need for such a buffer layer results in higher manufacturing cost and more complications in device processing and operation. CVD a-C:F layers also contain hydrogen impurities due to the use of hydrocarbon sources (e.g., CH.sub.4, C.sub.2 H.sub.2). Such hydrogen impurities tend to degrade the usefulness of the resultant material by reducing the thermal stability, due to disruption of the C--C crosslinking structure and the relative weakness of the C--H bond. An attempt at a partial solution to these CVD-related problems is reflected in T. Amano et al., "Preparation of fluorinated amorphous carbon (a-C:F) by magnetron sputtering," 58th Conference on Applied Physics of Japan, 1997. The authors describe an essentially hybrid CVD/sputtering approach (reactive sputtering) in which a CF.sub.4 gas source and a solid carbon source are used to form the a-C:F layer. Such an approach addresses problems created by hydrogen impurities, but does not appear to address the other problems encountered with CVD processes.
Thus, a-C:F layers are desired which exhibit low dielectric constant along with other required properties, and which are capable of being formed from processes more controllable than previous methods.